The present invention relates to a method for fabricating an amorphous-silicon thin film transistor, and more particularly to a method for forming its gate insulation layer.
FIG. 1 and FIG. 2 show structures of conventional amorphous-silicon thin film transistors which form an active layer using an amorphous silicon.
FIG. 1 is an amorphous-silicon thin film transistor having a back channel etch type and FIG. 2 is an amorphous-silicon thin film transistor having an etch stopper type.
Referring to FIG. 1, a method for fabricating the conventional amorphous-silicon thin film transistor shown in FIG. 1 will be hereinafter described.
As shown in FIG. 1, a metal thin film is first deposited on a glass substrate 11 and then patterned by a photolithography and etch process to form a gate electrode having sloped edges and a fixed pattern.
A gate insulation layer 13 is formed on the glass substrate 11 on which the gate electrode 12 is formed.
At this time, the gate insulation film 13 is formed as a singe film, double-layered film or triple-layered film.
The single film of gate insulation film 13 is formed of a silicon nitride thin film(SiNx) which is deposited by a Plasma Enhanced Chemical Vapour Deposition(PECVD) method and the double-layered film of gate insulation film 13 is formed of an silicon oxide film(SiO2) which is deposited by a thermal chemical vapour deposition(CVD) method or a sputtering method and a silicon nitride film(SiNx) which is deposited by a PECVD method, that is, as the structure of SiO2/SiNx.
The triple-layered film of gate insulation film 13 is formed of a metal-oxide film, an silicon oxide film and a silicon nitride film, for example, as the structure of Al2O3/SiO2/SiNx or Ta2O5/SiO2/SiNx.
After the gate insulation film 13 is formed, as above-mentioned, an amorphous silicon film 14 is deposited on the gate insulation film 13 by a PECVD method as an active layer and a n+ type amorphous silicon film 15 is then deposited as an ohmic layer.
Thereafter, the amorphous silicon film 14 and the n+ amorphous silicon film 15 are patterned with a fixed pattern.
Subsequently, a metal is deposited and patterned to form source and drain electrodes 16 and the n+ type amorphous silicon film 15 is subjected to an etching process to remove the portion exposed between the source and drain regions 16.
Finally, a passivation film 17 is deposited over the glass substrate 11, thereby obtaining a TFT.
Referring to FIG. 2, a method for fabricating the conventional amorphous-silicon thin film transistor shown in FIG. 2 will be hereinafter described.
As shown in FIG. 2, a gate electrode having sloped edges 22 is formed on a glass substrate 21 and a gate insulation layer 23 is then formed on the glass substrate 21 where the gate electrode 22 is formed.
At this time, an amorphous silicon film 24 is deposited on the gate insulation layer 23 and an insulation layer 25 is then deposited on the amorphous silicon film 24 as an etch stopper layer.
The insulation film 25 is etched by a photolithography and etching process, so as to form a pattern on a portion of the amorphous silicon film 24 corresponding to the upper surface of the gate electrode 22.
Upon etching the portion of the n+ type amorphous-silicon film exposed between the source and drain electrodes, after forming them, the insulation film 25 serves as an etch stopper layer for preventing a portion of the amorphous silicon film 24 located under the n+ type amorphous silicon film from being etched.
Thereafter, a n+ type amorphous silicon film 26 is deposited over the glass substrate 21 and then the amorphous silicon film 24 and the n+ type amorphous silicon film 26 are etched in this order so as to remain the n+ type amorphous silicon film 26 and the amorphous silicon film 24 merely at the upper side of the gate electrode 22.
A metal is deposited over the glass substrate 21 and then subjected to a photolithography and etching process to form source and drain electrodes 27.
After the source and drain electrodes 27 are formed. a portion of the n+ type amorphous silicon film 26 exposed between the source and drain electrodes 27 is etched and removed using the remaining insulation film 25 as an etch stopper.
A passivation film 28 is finally formed over the whole surface of the glass substrate 21, thus obtaining an amorphous silicon TFT having an etch stopper type.
In fabricating the conventional thin film transistors, as above-mentioned, a silicon nitride film formed by a PECVD method is used with the structure of the single layer or the multi-layer as the gate insulation film.
The reason why the silicon nitride film is used as the gate insulation film is because the best boundary-characteristic between the gate insulation layer and the amorphous silicon film can be obtained upon forming the gate insulation film with a silicon nitride film, and also because the PECVD method for forming the gate insulation film is carried out at a low temperature of about 300 to 400 degrees C. and it is thus the most proper process in obtaining a good quality of silicon nitride thin film.
In case of forming a silicon nitride film with a PECVD method, however, there are disadvantages in that many particles may be generated during the PECVD process and moreover the failure rate of devices may be increased due to the generated particles since reaction of the gases used for PECVD is a plasma condition.
There are also disadvantages in that the fabrication speed is slow due to the characteristic of the PECVD method and the cost for fabricating thin film transistors gets increased since the apparatus for PECVD is expensive.